1. Field of the Invention
The invention relates generally to the fabrication of integrated circuits. The invention is directed more specifically to the formation of patterned metallization layers in electronic integrated circuits.
2a. Cross Reference to Publications in the Related Art
The following publications are believed relevant to the below discussion and are incorporated herein by reference.
(1) D. C. Thomas et al, "A Multilevel Tungsten Interconnect Technology," Tech Digest, IEDM 1988, pp 466-469. PA1 (2) J. S. H. Cho et al, "Copper Interconnection with Tungsten Cladding for ULSI," 1991 Symposium on VLSI Technology, Oiso, Japan, pages 32-40. PA1 (3) B. Rogers et al, "Issues in a Submicron Cu Interconnect System Using Liftoff Patterning," IEEE VMIC Conference Proceedings, June 1991, pages 137-143. PA1 (4) D. S. Gardner et al, "Encapsulated Copper Interconnection Devices Using Sidewall Barriers," VMIC Conference Proceedings, June 1991, pages 99-108. PA1 (5) J. A. T. Norman et al, "New OMCVD Precursors For Selective Copper Metallization," VMIC Conference Proceeding, June 1991, pages 123-129. PA1 (6) J. D. McBrayer et al, "Diffusion of Metals in Silicon Dioxide," J. Electrochem. Soc., Vol. 133, June 1986, pp 1242-1246.
2b. Description of the Related Art
Much like the copper wires that conventionally interconnect discrete components in breadboard circuits, metal connectors are used in integrated circuits (IC's) to provide interconnections between distant points of integrated semiconductor circuits.
Aluminum has been the metal of choice for silicon based IC's. A continuous layer of aluminum is first sputter deposited onto a silicon-based substrate and portions of the aluminum layer are thereafter photo-lithographically patterned and removed to define conductors of specific shapes and sizes.
The two step process of depositing a metal layer onto a substrate and etching away parts of the deposited layer is referred to here as the coat & remove process.
The coat & remove process suffers from a number of disadvantages. It wastes materials because excess metal is sputtered on and then removed. It wastes energy because the energy used to coat on the metal layer and later remove the same metal is energy that is nonproductive. The coat & remove process also suffers from low manufacturing yields due to complications in the patterning half of the process.
Modern designs call for conductors of very fine width and fine pitch (e.g. submicron line widths and submicron line spacings). Forming metal conductors of fine width and spacing without unwanted shorts or opens is difficult, particularly when the coat & remove process is utilized. If etching is carried out for too much time during the metal removal step, unwanted open circuits may develop. If etching is carried out for too short a time during the metal removal step, unwanted metal may be left behind to create undesired short circuits. There is a long felt need in the industry to find a better way than the metal coat & remove process for defining fine-width and fine-pitch metal connections.
In addition to the above mentioned specific problems of the coat & remove process, there are a number of other problems of particular concern to metallization in general: (1) good adhesion of the metal conductors to insulative materials, (2) avoidance of contamination from the metal material of deposited metal conductors to adjoining structures, and (3) ease of patternability.
These general concerns become paramount when the metal conductors include copper. Copper is notorious for: (1) its poor adhesion qualities to silicon dioxide, (2) its tendency to readily diffuse through dielectric materials such as silicon dioxide under certain process conditions and contaminate an underlying silicon region, and (3) its resistance to traditional dry-etch patterning methods (RIE or plasma etch). Aluminum does not have these drawbacks.
Despite these problems, there is a long felt desire within the industry to find ways of including copper within the metal interconnect structure of an IC instead of or in addition to aluminum. Copper has a lower resistivity than aluminum and a higher electromigration immunity. The signal propagation delay of copper conductors is smaller, and as such, copper conductors are preferred in high speed circuits.
There are three conventionally-proposed methods for placing copper conductors on silicon-based substrates. Neither method has met with much commercial success and both methods are still considered to be more in the nature of laboratory-experiments rather than mature mass-production techniques.
In the first conventional method, a continuous interfacial film made of one or more layers having refractory metals such as titanium or tungsten is sputter deposited onto a substrate surface in cases where the substrate surface is composed of silicon and/or silicon dioxide. The interfacial film typically includes a Ti adhesion layer for providing good adhesion to SiO.sub.2 and a TiW, TiN or Ti.sub.3 N.sub.4 barrier layer on top for blocking diffusion. After this, a continuous copper layer is sputter deposited onto the TiN/Ti interfacial film. The upper copper film is then patterned by means of a patterning step specific to copper. The lower TiN/Ti interfacial film is thereafter patterned using a patterning step specific to its respective barrier and adhesion layers (e.g., TiN and Ti).
In the second conventionally-proposed method, a continuous interfacial film composed of Ti/TiN for example is sputter deposited onto the substrate and patterned immediately thereafter. Copper is then selectively grown on the patterned material of the interfacial film. The copper material adheres to the patterned material of the interfacial film but not to any exposed silicon dioxide. The problem with this method, however, is that copper adheres to the sidewalls of the interfacial metal conductors thereby producing excessively wide lines. The resulting, uncontrolled profile of the copper-coated lines is generally not acceptable for mass production of high density integrated circuits (IC's).
In the third conventionally-proposed method, the interfacial film is simultaneously formed and patterned by depositing tungsten (W) selectively onto the Si/SiO.sub.2 surface using a CVD method. A major problem with this approach is that spurious nucleations tend to form shorts between adjacent lines.
The above described, conventionally-tried approaches have a number of overlapping problems. First, it is time-consuming and expensive to form a multi-layer interfacial film (e.g., TiN/Ti). Second, it is difficult to pattern copper with conventional dry-etch approaches. Third, even when a barrier metal layer (e.g., Ti.sub.3 N.sub.4) is employed, some copper manages to migrate into and through adjacent silicon dioxide material and to contaminate a neighboring layer of silicon.